For semiconductor manufacturing, especially for very large scale integrated (VLSI) circuits, the main device component is metal-oxide-semiconductor field-effect transistor (MOSFET). Since the invention of MOSFET, the geometric size of MOSFET has been continuously reduced following the Moore's law. However, the physical limits of devices may lead to increasing challenges in continuously scaling down the devices. Specifically, in the field of MOSFET manufacturing, the challenging aspect is a current leaking problem due to decreases in the thicknesses of the polycrystalline Si layer and the SiO2 dielectric layer in the traditional MOS technology as the devices are scaled down.
Aimed to solve the above problems, the current technology uses high-k (dielectric constant or permittivity) dielectric material to replace the traditional SiO2 dielectric material. In the meantime, the current technology also uses metal gate to match with the high-k dielectric material.
According to existing methods, during the formation of contact plugs in source/drain regions of a metal gate transistor, a number of factors, such as the size of the via and the overlay (OVL) offset in aligning the photomask and the substrate, may cause a short circuit between the metal gate and the formed contact plug in the source/drain region, which may reduce device yield. On the other hand, the size of the via and the OVL offset in aligning the photomask and the substrate may be reduced in order to improve device yield, but process cost may also be increased.
The disclosed fabrication method and metal gate transistor are directed to solve one or more problems set forth above and other problems in the art.